Computing on the GPU

Scalable Parallel Programming with CUDA on Manycore GPUs

Call for Book Chapters

With the emergence of multicore computers, we are facing the challenge of parallelizing performance-critical applications of all sorts. Compared to sequential applications, our repertoire of tools and methods for cost-effectively developing reliable, parallel applications is spotty. The purpose of this book is to capture the state-of-the-art of multicore software development and to make it accessible to reearchers, practitioners, and students of multicore software engineering.

Experts from all fields are invited to propose a Chapter covering a topic related to multicore software development. We also welcome submisions that address - from the software development point of view - issues multicore systems architecture, operating systems, as well as languages and compilers for multicore systems. The Chapters should address a general audience interested in current developments in the multicore area.

Possible topics include, but are not limited to:

• Multicore architectures
• Engineering issues of multicore processors
• Architectural features that may enhance the parallel performance
• Caching
• Parallel patterns
• Frameworks and libraries for multicore software
• Modeling techniques
• Parallel software architectures
• Software components and composition
• Programming languages/models for multicore software
• Compilers for parallelism
• Run-time issues such as garbage collection or thread scheduling
• Ways of specifying or hinting at parallelism
• Testing and debugging parallel applications
• Parallel algorithms and data structures
• Software reengineering for parallelism
• Transactional Memory
• Autotuning
• Operating system support, scheduling
• Visualization tools
• Development environments for multicore software
• Process models for multicore software development
• Experience reports from research or industrial projects

[IWMSE 08] Proceedings

The proceedings of 1st international workshop on Multicore software engineering are available online now.

"With the emergence of multicore computers, software engineers face the challenge of parallelizing performance-critical applications of all sorts. Compared to sequential applications, our repertoire of tools and methods for cost-effectively developing reliable, parallel applications is spotty. The purpose of this workshop is to bring together researchers and practitioners with diverse backgrounds in order to advance the state of the art in software engineering for multi/manycore parallel applications."

Here is an outline of the proceedings:

• Keynotes and Tutorials:
  • "Transactional memory: from semantics to silicon" Ali-Reza Adl-Tabatabai
  • "Putting intel threading building blocks to work" Thomas Willhalm, Nicolae Popovici
  • "Parallel computing with x10" PVR Murthy
• Sessions:
  • Parallel Libraries
  • Programming models and fault detection
  • Applications and experience reports

Photographs of the event are available on the workshop website as well.

First CUDA Center of Excellence Appointed by NVIDIA

NVIDIA Corporation, a leader in graphics technologies, announced yesterday, together with the University of Illinois at Urbana-Champaign (UIUC), that the University has been appointed as the world's first CUDA Center of Excellence. The Santa Clara company also made a $500,000 donation to UIUC, in addition to the appointment, to facilitate the development of parallel computing and to ensure the continuation of its research programs.

Workshop on Programming Massively Parallel Processors

The Institute for Advanced Computing Applications and Technologies at the University of Illinois at Urbana-Champaign is sponsoring a free one-day Workshop on Programming Massively Parallel Processors (PMPP)

PMPP will bring together researchers, industry, and users concerned with the issue of programming multi-core and many-core architectures for productive use in applications ranging from desktop to high-performance computing systems. The workshop will include presentations from industry leaders and early technology adopters and will stimulate the dialogue among researchers about programming models, languages, and tools that the community is lacking in order to take advantage of the emerging multi-core and many-core architectures. Topics will include:

• Novel chip multiprocessing architectures
• Programming models for massively parallel processors, algorithms, and formal methods
• Programming languages for multi- and many-core systems, compilers and tools
• Applications running on multi- and many-core systems

1st Annual UMD GPGPU Programming Contest

Despite the plethora of great work being done recently in General Purpose GPU programming, there are still many common tasks for which there is no publicly available code to be found online. We feel that this inhibits the progress of Science by forcing people to reinvent the wheel far too often. Furthermore, the verification through reproducibility that is so critical to the Scientific process is nearly impossible without open source code.

In order to improve this situation, we are sponsoring a GPGPU programming contest, and will be releasing the entries, at the conclusion of the contest, under version 3 of the GPL

The particular task we are asking contestants to address is sparse matrix multiplication. We'll be evaluating entries on both vector/sparse matrix and sparse matrix/sparse matrix multiplications, using a variety of different inputs.

As the contest progresses, we'll be updating the LeaderBoard regularly, so contestants will have some idea of where they stand. Contestants are welcome to make as many entries as they want, so we encourage you to submit early and tweak your design. We will, however, ask you to register a user account so we can keep track of a version history of all of your submissions.

[IFMT'08] CALL FOR PAPERS

With the tremendous advances in process technology and the non-scalability of complex monolithic designs, multicore architecture is becoming the design of choice for high-end machines to embedded devices. The number of cores per chip is expected to grow, even to double, every two years. Although these advances are providing us with a lot of opportunities, they are also giving us a lot of design challenges, such as bandwidth requirement, power (both static and dynamic), memory wall, parallelization, etc.

This forum aims to provide an avenue to foster communication among academia and industry in all aspects of next-generation multicore technologies, such as the Cell BE processor. Authors are invited to submit high quality papers representing their original work in (but not limited to) the following topics targeting muticore/manycore processors:

• Parallel Programming Models
• Specific applications
• Performance modeling and analysis
• Memory management and models (including software caching and prefetching)
• Thread management and Thread-level speculation (including scheduling and load-balancing)
• Cache hierarchy design
• Interconnection and network on chip
• Power-aware design
• Simulation tools
• Compilation techniques
• Homogeneous and heterogeneous architectures
• Security issues

Workshop: Effective Use of the TeraGrid's Multi-core Systems

The National Center for Supercomputing Applications at the University of Illinois in Urbana-Champaign is hosting a bring-your-own-code workshop on the "Effective Use of the TeraGrid's Multi-core Systems" on August 5-7, 2008.

This workshop will provide current users of the TeraGrid's multi-core systems an understanding of multi-core technology and how to leverage it to accelerate their science and engineering research. Topics presented will include an overview of multi-core performance issues, performance tuning examples and lessons learned. In addition, NCSA consulting and application support staff will provide hands-on assistance to participants to help them port and tune their applications on the multi-core systems.

This workshop will be limited to twenty (20) participants selected by an application process. Preference will be given to current TeraGrid users with allocations on systems with multi-core processors (e.g. Abe, Big Red, Ranger) and application code and sample data available for testing and tuning during the workshop.

[PPoPP 08] Proceedings

The proceedings of 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming are available online now.

"The goal of the PPoPP Symposia is to provide a forum for papers on the principles and foundations of parallel programming, tools and techniques for parallel programming, and experiences in using parallel programming to solve applications problems."

Here is an outline of the proceedings:

Keynote: "Compilers and parallel computing systems" Frances Allen

• Sessions:
  • Static analysis
  • Parallel algorithms
  • Matrix product for special platforms
  • GPUs and SIMD
  • Programming model extensions
  • Runtime systems
  • Formal aspects of transactions & speculation
  • Transactional memory I
  • Transactional memory II: STM implementation
• Panel: "Where will all the threads come from?" John Mellor-Crummey
• Posters